Synchronous interface for a nonvolatile memory
US6564285B1 · kind B1 · utility
331Cited by
65References
18Claims
0Family size
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Key dates
| Filing date | Jun 14, 2000 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.