Method and apparatus for defining cacheable address ranges
US6564299B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Oct 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addressable circuit configured to control a definition of an addressable range for the circuit. The circuit may comprise at least one register, at east one flag, an input and control logic. The register may be configured to define a range used for determining an addressable range for the circuit. The flag may be configured to define whether a predetermined range is to be inverted for determining the addressable range for the circuit. The input may be configured to receive an address for an access to the circuit. The control logic may be configured to process the received address to determine whether the received address is within the addressable range for the circuit, the control logic being responsive to the register and to the flag for determining the addressable range therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.