Dual port memory for digital signal processor
US6564303B1 · kind B1 · utility
0Cited by
13References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1998 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a data processing system comprising a processor provided with two memory access units operating in parallel; two separate memories respectively associated with the two access units; and circuitry for, when the address of a datum to be written into a memory is in a predetermined address range, writing the datum into both memories at the same time at the same address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.