DSP architecture optimized for memory accesses
US6564309B1 · kind B1 · utility
4Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 6, 1999 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Apr 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a processor including at least one memory access unit for presenting a read or write address over an address bus of a memory in response to the execution of a read or write instruction; and an arithmetic and logic unit operating in parallel with the memory access unit and arranged at least to present data on the data bus of the memory while the memory access unit presents a write address. The processor includes a write address queue in which is stored each write address provided by the memory access unit waiting for the availability of the data to be written.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.