Method and apparatus for reducing code size by executing no operation instructions that are not explicitly included in code using programmable delay slots
US6564316B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1999 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Sep 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a state machine made up of a delay slot path and a no operation path, both made up of nodes with arcs connecting between them. There are arcs between the nodes of the delay slot path and the nodes of the no operation path. The number of nodes in the no operation path is equivalent to the number of available delay slots. The path taken for a specific instruction along the delay slot path, the no operation path and the arcs depends on the number of delay slots which the specific instruction utilizes. There is also disclosed a method for executing non-sequential instructions as performed by the state machine of the present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.