Cross chip transfer mechanism for a memory repeater chip in a Dram memory system
US6564335B1 · kind B1 · utility
7Cited by
3References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a method of transferring data across a semiconductor chip comprises transmitting data from a first Rambus asic cell to a second Rambus asic cell using clock pulses generated at a first clock generator and sampling the data at the second Rambus asic cell using clock pulses generated at a second clock generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.