Fault tolerant virtual VMEbus backplane design
US6564340B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1999 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Nov 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides fault tolerant capability for a Versa Module Eurocards backplane system design for high reliability applications. An approach of connecting two independent backplanes together electrically, but providing isolation capabilities in the event of a failure was developed. The electrical connection or integrated bridge design provides a virtual connection between the two VME backplanes that is transparent to the end user. The integrated virtual VMEbus design provides a low latency, high bandwidth interconnect between modules whether located on the same local bus or the electrically isolateable bus. This dual-VME fault tolerant backplane design eliminates complete system failures due to single event failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.