Method and apparatus for storing and using chipset built-in self-test signatures
US6564348B1 · kind B1 · utility
53Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1999 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Nov 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for storing and using chipset built-in self-test (BIST) signatures is provided. A BIST for a chip in a data processing system may be initiated by a power-on-reset in the data processing system. The BIST signature generated during the BIST is compared with a predetermined BIST signature stored in a vital products data (VPD) module associated with the chip is read. A difference between the generated BIST signature and the predetermined BIST signature is then reported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.