System and method for analyzing simultaneous switching noise
US6564355B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2000 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Nov 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for analyzing simultaneous switching noise. In one embodiment, a model may be provided for the electronic circuit to be analyzed. The electronic circuit may be an integrated circuit, a multi-chip module, a printed circuit assembly, or other type, and may in some embodiments include combinations of these types. The electronic circuit may include a plurality of drivers, each of which may be coupled to a power plane, a ground plane, and a transmission line. The connection of the driver may be accurately modeled in this manner. Each driver may be configured to switch between a logic high voltage and a logic low voltage. The modeled electronic circuit may also include a voltage source coupled to the power plane and the ground plane, a voltage regulator module, and a plurality of decoupling capacitors. The simultaneous switching of a plurality of drivers, from a logic high to a logic low, or vice versa, may be simulated. The system and method may then allow for the calculation of solutions for the transmission line and the power planes (as will be detailed below). The transmission line solution and power plane solution may be superimposed on each other, which may allo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.