Flash memory array structure and method of forming

US6566200B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Freidoon Mehrad · Plano, US
• Suresh Potla · Dallas, US
• Zhihao Chen · Yueqing, CN

Key dates

• Filing date: Jun 20, 2002
• Grant date: May 20, 2003
• Expiry date: Jun 20, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.