Method of fabricating semiconductor device
US6566232B1 · kind B1 · utility
38Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Oct 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
After a silicon oxide film is formed on a semiconductor wafer, pattern formation alignment marks are provided in the chip formation areas and through-holes for stacking are formed in each chip formation area using an alignment mark as reference in order to improve accuracy in vertically stacking semiconductor chips. Next, after forming elements, wiring and electrode parts on the semiconductor wafer, the semiconductor wafer is cut along the chip formation area and is divided into semiconductor chips. Then, the divided semiconductor chips, as many as needed, are stacked by matching the through-holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.