Transistor, semiconductor memory and method of fabricating the same
US6566707B1 · kind B1 · utility
16Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1998 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Dec 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of source/drain regions are formed on a surface of a silicon substrate at a prescribed space. Floating gate electrodes are formed on sides of a channel region closer to the source/drain regions respectively through a first insulator film. Projections are formed on peripheral edge portions of the floating gate electrodes respectively. A control gate electrode is formed over the channel region and the floating gate electrodes through a second insulator film. The control gate electrode is opposed to the floating gate electrodes at one surface through the second insulator film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.