Semiconductor storage device having memory chips in a stacked structure
US6566760B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 19, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Sep 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.