Output conductance correction circuit for high compliance short-channel MOS switched current mirror
US6566851B1 · kind B1 · utility
9Cited by
6References
21Claims
0Family size
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Inventors
Key dates
| Filing date | Aug 10, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Dec 15, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A high-speed current mirror and correction circuitry are provided to minimize current errors in short-channel MOS switched current mirrors. The current mirror supplies high current levels at high modulation speeds, while simultaneously exhibiting good output voltage compliance. The correction circuitry includes a buffer amplifier, current shaping circuit, and replica mirror section. The current shaping circuit is able to supply a differential reference current, to correct load current errors, in response to the replica mirror section matching the buffered load voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.