Zero phase and frequency restart PLL
US6566922B1 · kind B1 · utility
8Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Oct 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/101
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit generally comprising a first circuit and a phase lock loop. The first circuit may be configured to (i) collect a plurality of samples per cycle during a plurality of cycles of an input signal and (ii) calculate a phase offset and a frequency offset for the input signal relative to a clock signal in response to the samples. The phase lock loop may be configured to (i) preset a phase error signal to the phase offset and a frequency error signal to the frequency offset and (ii) generate the clock signal in response to the phase error signal and the frequency error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.