Configurable triple phase-locked loop circuit and method
US6566967B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2002 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Feb 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.