Design-for-test circuit for successive approximation analog-to-digital converters
US6567021B1 · kind B1 · utility
8Cited by
9References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Aug 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method (30) of testing analog-to-digital converters (ADCs) (12) that shortens the test time required to measure INL and DNL by advantageously converting the ADC (12) into a digital to analog converter (DAC) (10). The conversion from ADC to DAC is accomplished using a DfT test mode, which reconfigures the ADC into a DAC using a delta modulation circuit. Since DACs can be tested much more efficiently than ADCs, the ADC test time is substantially reduced by the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.