High-speed low-power semiconductor memory architecture
US6567290B2 · kind B2 · utility
7Cited by
7References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.