Nonvolatile semiconductor memory with improved sense amplifier operating margin
US6567310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2002 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Mar 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Nonvolatile semiconductor memory has a core-side cell array having word lines, bit lines and memory cells; a reference-side cell array having word lines, bit line, and reference cell; and, a sense amplifier which compares a core-side input voltage corresponding to a bit line current in the core-side cell array, and a reference-side input voltage corresponding to the bit-line current in the reference-side cell array. The core-side decoder-driver and reference-side decoder-driver drive the core-side and reference-side word lines to the power supply voltage at a first time at the end of the address change detection pulse, and, at a second time a prescribed time after the end of the address change detection pulse, drive the core-side and reference-side word lines to a boost voltage level higher than the power supply voltage. The sense amplifier begins comparison of the core-side and the reference-side input voltages after the second time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.