Pulsed circuit topology to perform a memory array write operation
US6567337B1 · kind B1 · utility
8Cited by
31References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulsed circuit topology to perform a memory array write operation. A write enable pulse width control circuit is responsive to a pulsed clock signal to generate a pulsed write enable signal and a write data path circuit is provided to output a write data signal. The write enable pulse width control circuit and the write data path circuit together control a write operation to a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.