Memory storage cell based array of counters
US6567340B1 · kind B1 · utility
91Cited by
78References
56Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Apr 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/56
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-counter based system having a counter array. Each counter of the array having a memory cell. The system also includes an address decoder coupled to the counter array to select at least one of the memory cells within the counter array and read/write circuitry coupled to the counter array to pass data with the counter array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.