Use of static noise analysis for integrated circuits fabricated in a silicon-on-insulator process technology
US6567773B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1999 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Nov 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for analyzing the effect of electrical noise in an integrated circuit fabricated in a silicon-on-insulator (“SOI”) technology. The present invention uses a static noise analysis to evaluate an integrated circuit's response to electrical noise, taking into account hysteresis effect and parasitic bipolar current voltage, both of which are unique to integrated circuits fabricated in a SOI technology process. The present invention also includes a computer, computer storage device, computer program and software incorporating the method steps and simulating the testing and analysis of the circuit under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.