Implementation of multipliers in programmable arrays
US6567834B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Jun 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided a method of multiplying a first number by a second number by use of an array of processing devices, each of said processing devices having a plurality of data inputs, a plurality of data outputs, and an instruction input for control of the function of the processing device, wherein said processing devices and an input for the first number and an input for the second number are interconnected by a freely configurable interconnect, and wherein each processing device calculates a partial product for multiplication of one or more bits of the first number with one or more bits of the second number, and for each processing device: the value received at the instruction input is determined by one or more bits of the first number; data inputs are provided by m bits of the second number, and, if appropriate, a carry input to add a carry from a less significant partial product and/or a summation input to sum all the partial products of the sa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.