Method and apparatus for repeating (extending) transactions on a bus without clock delay
US6567871B2 · kind B2 · utility
3Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1999 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Jul 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is described that is related to repeating (extending) transactions on a bus. A plurality of buffer pairs are configured to direct a plurality of signals between a first bus and a second bus in a bus cycle. A circuit is configured to monitor a control signal to determine a bus location of a master device and the circuit is further configured to enable one buffer in the buffer pairs to control a direction of the plurality of signals between the first bus and the second bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.