Management of resets for interdependent dual small computer standard interface (SCSI) bus controller
US6567879B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Nov 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first SCSI bus, a second SCSI bus, a first bus controller slot, a second bus controller slot and a bus controller in one of the first bus controller slot and the second bus controller slot. The bus controller includes reset circuitry for generating a SCSI bus reset signal. The SCSI bus reset signal being used to reset the first SCSI bus when the bus controller is in the first bus controller slot and the first SCSI bus is isolated from the second SCSI bus. The SCSI bus reset signal being used to reset the second SCSI bus when the bus controller is in the second bus controller slot and the first SCSI bus is isolated from the second SCSI bus. The SCSI bus reset signal is to reset both the first SCSI bus and the second SCSI bus when the first SCSI bus and the second SCSI bus are bridged and one of the following conditions is met: the bus controller is in the first bus controller slot, or the bus controller is in the second bus controller slot and the first bus controller slot is empty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.