Methods and arrangements for improved stripe-based processing
US6567891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Jun 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. Parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC). The ASIC includes one or more local result buffers for holding intermediate computation results, one or more mathematical operator components configured to receive data strips, which are portions of larger data stripes, coefficients associated with the data strips, and operates on them to provide intermediate computation results that can be written to the local result buffers Upon completing the parity processing of a strip, the results are then stored in an external memory (e.g., RAM). U…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.