Method and apparatus for set associative cache tag error detection
US6567952B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Apr 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of error detection circuits. Each of the plurality of error detection circuits is coupled to one of a like plurality of ways in a set associative cache memory to receive a tag word and an error detection flag from the coupled way. Each of the plurality of error detection circuits generates a way error signal that is asserted if an error is detected in the tag word of the coupled way. A logical OR circuit is coupled to the plurality of error detection circuits to receive the plurality of way error signals. The logical OR circuit generates a tag error signal that is asserted if at least one of the plurality of way error signals is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.