Method and device for verification of VLSI designs
US6567959B2 · kind B2 · utility
11Cited by
22References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Apr 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a formal equivalence verification method and system to determine the compatibility, or nonsimilarity, of two or more circuit designs. The method and system can check the corresponding verification nodes or candidates for cut points while accounting for input vectors including environmental conditions. The method and system may produce an answer for the user to indicate, for example, compatibility or disimilarity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.