Interweaved integrated circuit interconnects
US6567966B2 · kind B2 · utility
2Cited by
13References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | May 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are presented for decreasing the effect of Miller capacitance on adjacent interconnects in an integrated circuit. The systems and methods include interweaving interconnects with signals traveling in one direction with interconnects with signals traveling in the opposite direction. The systems include a system for fabricating integrated circuits with interweaved interconnects and an integrated circuit with interweaved interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.