Method for designing large standard-cell base integrated circuits

US6567967B2 · kind B2 · utility

Assignee

• Monterey Design Systems, Inc. · US

Inventors

• Yaacov Greidinger
• David S. Reed · Los Altos, US
• Ara Markosian · Cupertino, US
• Stephen P. Sample · Saratoga, US
• Jonathan Frankle · Los Gatos, US
• Hasmik Lazaryan · Yerevan, AM

Key dates

• Filing date: Jun 4, 2001
• Grant date: May 20, 2003
• Expiry date: Jun 4, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/3947
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.