Block level routing architecture in a field programmable gate array
US6567968B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 6, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Mar 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Block (EB) 3×3 switch matrix. A second side of each EB…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.