Semiconductor wafer finishing control
US6568989B1 · kind B1 · utility
25Cited by
67References
64Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Mar 29, 2020 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24B49/04
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A method of in situ control for finishing semiconductor wafers to improve cost of ownership is discussed. A method to use business calculations combined with physical measurements to improve control. The use of boundary lubricating layer control in the operative finishing interface and business calculations to improve the cost of finishing semiconductor wafers is discussed. The method aids control of differential lubricating boundary layers and improved differential finishing of semiconductor wafers. Planarization and localized finishing can be improved using differential lubricating boundary layer methods of finishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.