Triple layer isolation for silicon microstructure and structures formed using the same
US6569702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Jul 15, 2021 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0178
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An isolation method for a single crystalline silicon microstructure using a triple layer structure is disclosed. The method includes forming the triple layer composed of an insulation layer formed over an exposed surface of the silicon microstructure, a conductive layer formed over the entire insulation layer, and a metal layer formed over a top portion of the microstructure; and partially etching the conductive layer to form electrical isolation between parts of the microstructure. The method does not require a separate photolithography process for isolation, and can be effectively applied to microstructures having high aspect ratios and narrow trenches. Also disclosed are single crystalline silicon microstructures having a triple layer isolation structure formed using the disclosed method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.