Method of manufacturing a thin film transistor to reduce contact resistance between a drain region and an interconnecting metal line
US6569721B1 · kind B1 · utility
0Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Nov 8, 1999 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A thin film transistor includes a low resistance metal film covering a drain region and an interconnecting metal line disposed thereon. Covering the drain region with the low resistance metal film reduces oxidation in the drain region, and thus reduces the contact resistance between the drain region and the interconnecting metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.