Semiconductor device with varying width electrode
US6570231B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Aug 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
Abstract
An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.