Method and circuit for pre-emphasis equalization in high speed data communications
US6570406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Nov 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0288
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude. The amount of amplitude change from full scale back to mid-scale determines the amount of equalization to be provided by the output buffer to the transmission channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.