Frequency dividing circuit
US6570417B2 · kind B2 · utility
5Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Oct 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/546
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.