Phase difference signal generator and multi-phase clock signal generator having phase interpolator
US6570425B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Nov 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a phase difference signal generator, a first delay circuit has a delay time of nx where n ix 2, 3, . . . and x is a voluntary real number, the delay circuit receiving a first input clock signal having a phase of 0° to generate a first phase difference signal. At least one k-to-(n−k) weighted phase interpolator has a first input for receiving an output signal of said first delay circuit and a second input for receiving a second input clock signal having a phase of &thgr; to generate an output signal having a phase of (n−k)x+k&thgr;/n where k is 1, 2, . . . , n−1. At least one second delay circuit is connected to the k-to-(n−k) weighted phase interpolator. The second delay circuit has a delay time of kx to generate a k-th phase difference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.