Clock generator for generating internal clock signal synchronized with reference clock signal
US6570456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2002 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | May 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal according to a phase difference in a first phase-locked loop is transferred to a power supply line as an operation power supply voltage for a first oscillation circuit included in the first phase-locked loop. The potential of the power supply line is supplied to a second oscillation circuit in a second phase-locked loop as an operation power supply voltage. The second phase-locked loop is used to generate a clock signal phase-synchronized to the input clock signal. Consequently, a clock generator is implemented that oscillates at a central frequency to generate a recovered clock signal even when a variation is caused in a manufacturing parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.