Multistage scrambler for a digital to analog converter
US6570521B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Dec 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multistage scrambler for a digital to analog converter having a non-ideal transfer function resulting from an error function which causes harmonic distortion includes a first shuffling network having a first input for receiving digital data and a first output, the first shuffling network including a first set of data switches; a first sequence generator for selectively interconnecting the first set of data switches to reorder at the first output the digital data received at the first input to reduce the harmonic distortion to lower magnitude colored noise; a second shuffling network having a second input for receiving the reordered digital data from the first output and a second output, the second shuffling network including a second set of data switches; and a second sequence generator for selectively interconnecting the second set of data switches to reorder at the second output the digital data received at the second input to transform the colored noise toward lower power white noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.