Semiconductor memory device
US6570802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Nov 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to an output signal from the timer circuit. The first internal address generation circuit generates a refresh address of the entire memory region, and the second internal address generation circuit generates a refresh address of a certain part of the regions. By carrying out refresh of only a part of the memory required to be retained, the electric power consumption can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.