Three-state differential data transmission with self latching ability
US6570930B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 27, 1998 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | May 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/38
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Digital data transmission using three logic states on a differential pair of signal lines. The three states are: a first line a threshold higher than a second line, the second line a threshold higher than the first line, and when both lines are approximately equal. The presence of three states allows the receiving circuit to recognize the beginning and end of a valid data bit. A receiving circuit using two comparators to generate strobes for latching the data is also disclosed. The strobes also clock a counter whose output is fed to a decoder. The output of the decoder is used to select one of N latches that are used to latch the incoming data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.