Digital clocking synchronizing mechanism
US6570982B1 · kind B1 · utility
1Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/1334
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A telephone switching system regenerates a clock signal transmitted from control equipment to peripheral equipment. The switching system receives a clock signal from the control equipment at the peripheral equipment. The clock signal is compared to a reference clock signal generated at the peripheral equipment to determine a phase error. The phase error is accumulated over a time period as determined by the peripheral equipment. The system adjusts the modulo of a ring counter as a function of the accumulated phase error. The output of the ring counter can then be used in timing functions within the peripheral equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.