Method for acquiring FMAC rounding parameters
US6571266B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating-point multiply accumulate method acquiring a final mantissa result comprises comparing exponents of (A*B) and C. Transferring part of the C mantissa to a CHI register. Shifting any part of the C mantissa which overlaps the range of the (A*B) mantissa to align the bits of the (A*B) and C mantissas. Adding the shifted part of the C mantissa to the (A*B) mantissa. Shifting least significant bits corresponding to a number of bits transferred to the CHI register out of the Temp. Result. Mask merging bits of the C mantissa which were transferred to the CHI register with most significant bit positions of the shifted Temp. Result. Rounding this mantissa result to the first precision and acquiring L from an Lbit value of the CHI register or an Lbit value of the Temp. Result based on the bit value of the merge mask corresponding to the Lbit position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.