High speed device emulation computer system tester
US6571357B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The application discloses a system and method for providing a compact and high speed mechanism for emulating an ASIC or other chip operating within a large computing system environment for diagnostic purposes. A two step process is disclosed for generating data patterns for fully exercising a chip and to then transmit these data patterns at a high frequency to a system under test. In phase one, a pattern generator preferably transmits test pattern data at a first frequency to a memory storage device. In phase two, the memory storage device is enabled to transmit the stored test pattern data at a high frequency to a system under test. Buffering the test pattern data in this manner enables the inventive system to bypass the data transmission speed limitation of the pattern generator while still employing the test patterns created by the pattern generator and to thereby test the system under test under high speed operating conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.