Cage for dynamic attach testing of I/O boards
US6571360B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1999 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Oct 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2733
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested. The error cage isolates correction code errors, parity errors, protocol errors, timeout errors, and other similar errors generated by the I/O board under test. The address transaction cage isolates out of range memory addresses from the I/O board under test. The interrupt transaction cage isolates interrupt requests to an incorre…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.