Determining dependency relationships among design verification checks
US6571375B1 · kind B1 · utility
16Cited by
6References
79Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | May 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, multiple design verification checks associated with a hardware design are linked by determining dependency reationships among the multiple design verification checks. Each of the design verification checks represent a condition that must hold true in order for the hardware design to operate in accordance with an intended flow of logical signals in the hardware design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.