Semiconductor integrated circuit and semiconductor integrated circuit wiring layout method
US6571379B2 · kind B2 · utility
194Cited by
3References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Jun 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit includes a first wiring layer formed in a first direction, a second wiring layer formed in a second direction perpendicular to the first direction, and a third wiring layer formed in the second direction to sandwich the first wiring layer between the third wiring layer and the second wiring layer. The second and third wiring layers are shifted from each other by a predetermined distance in the first direction. An automatic layout method for a semiconductor integrated circuit, and a recording medium are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.