Method and computer program product for global minimization of sign-extension and zero-extension operations
US6571387B1 · kind B1 · utility
10Cited by
6References
9Claims
0Family size
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Key dates
| Filing date | Feb 8, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Feb 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer program product, within an optimizing compiler, for the global minimization of sign-extension and zero-extension operations in generated code during compilation. The method and computer program product allows, for example, 64-bit compilers targeting the Intel IA64 architecture to improve their SPECint benchmarks by reducing the number of sign-extension and zero-extension operations in the global and intra-procedural scope, thus, speeding up the execution of the compiled program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.