Integrated circuit package with EMI containment features
US6573590B1 · kind B1 · utility
21Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2002 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package comprising EMI containment features. The EMI containment features include a first EMI containment configuration and a second EMI containment configuration. The second EMI containment configuration is disposed around the first EMI containment configuration. The first and second EMI containment configurations include vias coupled to at least one ground plane of the integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.